Enlarge / SiFive’s “Important” household is stripped right down to the minimal configurations and efficiency obligatory for normal microcontroller responsibility. “Intelligence” provides AI/ML acceleration, and the brand new “Efficiency” household provides simply what it says on the tin.

At this time, RISC-V CPU design firm SiFive launched a brand new processor household with two core designs: P270 (a Linux-capable CPU with full help for RISC-V’s vector extension 1.0 launch candidate) and P550 (the highest-performing RISC-V CPU up to now).

A fast RISC-V overview

For these not instantly conversant in RISC-V, it’s a comparatively new CPU structure which takes benefit of Diminished Instruction Set Pc (RISC) ideas. RISC-V is an open commonplace particularly designed to be forward-looking and evade as a lot legacy cruft as potential. One instance of this design is RISC-V’s dynamic width vector instruction set, which permits builders to execute vector directions on knowledge of arbitrary measurement with most effectivity.

In conventional processor designs, a vector instruction has a set width tied to the {hardware} register measurement of the processor—for instance, SSE and SSE2 enable use of a Pentium III’s 128-bit registers, whereas making full use of an i7-4770’s 256-bit registers requires a totally separate instruction set (AVX2) for a similar mathematical operations. Shifting as much as an i7-1065G7’s 512-bit registers requires one more instruction set, AVX-512—once more, for a similar underlying mathematical operations.

In sharp distinction, RISC-V vector math permits a single set of CPU directions to carry out the identical set of mathematical operations as effectively as potential, utilizing no matter measurement registers the present CPU design has obtainable. This implies a developer can merely write a single routine that may course of vector operations as effectively as potential on a telephone with 64-bit registers or on a supercomputer with 1,024-bit registers.

Along with forward-looking options constructed into the RISC-V spec, the structure is designed to offer flexibility that its designers didn’t or couldn’t consider forward of time. Generic RISC-V designs function reserved opcodes, which designers of particular RISC-V CPUs could then take over to offer further, arbitrary performance.

The power to “take over” reserved opcodes permits for significantly streamlined ASIC design, since each specialised directions and basic controller performance will be supplied on a single die—and with out CPU architects needing to reinvent any wheels to offer the generic controller performance.

For the second, RISC-V shouldn’t be a critical competitor to both Arm or x86 within the general-purpose processor area, nevertheless it’s closely used within the microcontroller area, due partly to its extensibility and cheap licensing. We do broadly count on RISC-V to turn out to be a 3rd main participant in relation to general-purpose CPUs—the type that present the “foremost mind” for telephones, tablets, and conventional computer systems—however that’s nonetheless some years away.

What’s new within the SiFive Efficiency household?

The 2 new designs introduced right this moment are P270 and P550. P270 is SiFive’s first CPU to totally help the elective RISC-V vector extension 1.0 launch candidate, and P550 is SiFive’s highest-performing RISC-V processor up to now—additionally making it, so far as we all know, the highest-performing RISC-V processor obtainable.

P270 and “V” 1.0-rc1

SiFive's Recode automatically translates legacy SIMD source to SiFive vector assembly—in this case, beginning with source code written for Arm's Neon instruction set.
Enlarge / SiFive’s Recode routinely interprets legacy SIMD supply to SiFive vector meeting—on this case, starting with supply code written for Arm’s Neon instruction set.

As you’d count on from the “launch candidate” rider, RISC-V’s “V” elective instruction set shouldn’t be but a frozen commonplace. When the V spec reaches 1.0—with out the “launch candidate” rider—will probably be thought of secure sufficient to freeze the function set. It will enable builders to start work on long-term initiatives utilizing it for toolchains, purposeful simulators, and so forth, with a point of certainty that the code the builders have written will “simply work” on future CPU designs.

It is price noting that even as soon as the discharge candidate tag is eliminated, the 1.0 model of the V directions will nonetheless solely be thought of prepared for public ratification. The primary true manufacturing model of V can be 2.0, a model quantity awarded after public ratification is taken into account full, with no main performance modifications obligatory.

SiFive additionally provides a translation utility known as Recode, which routinely converts legacy SIMD code to V-spec vector meeting.

P550 excessive efficiency

This somewhat confusing trio of bar graphs shows a single P550 core significantly outperforming an equivalent Cortex A75 core (top two graphs) while blowing it out of the water in performance per on-die square millimeter (bottom graph).
Enlarge / This considerably complicated trio of bar graphs reveals a single P550 core considerably outperforming an equal Cortex A75 core (high two graphs) whereas blowing it out of the water in efficiency per on-die sq. millimeter (backside graph).

Each P270 and P550 are Linux-capable designs, however the P270 is restricted to a dual-issue, in-order pipeline with solely eight phases. Whereas the P270’s full V extension help ought to make it a formidable processor for closely vector-math-dependent functions, the P550 ought to show way more highly effective for functions nearer to these presently dealt with by general-purpose CPUs.

SiFive’s new Efficiency P550 core encompasses a 13-stage, triple-issue, out-of-order pipeline. SiFive claims {that a} four-core P550-based CPU takes up roughly the identical on-die space as a single Arm Cortex-A75, with a major efficiency benefit over that competing Arm design. SiFive says the P550 delivers 8.65 SPECInt 2006 per GHz, based mostly on inside engineering take a look at outcomes—a laudable consequence when in comparison with Cortex-A75 (and never too far behind an i9-10900K’s 11.08/GHz). But it surely’s nicely behind an Apple A14’s 21.1/GHz.

Intel adopts P550 to be used in its Horse Creek platform

Before everything, we have to make one factor clear—we’re nearly definitely not speaking about Intel ditching the x86_64 structure for RISC-V! Fashionable x86_64 CPUs from Intel and AMD embrace administration and supervisory cores, which aren’t straight accessible to finish customers. These are usually Arm CPU cores; for instance, AMD’s first APUs used Cortex-A5 for his or her platform safety processor.

The joint announcement from Intel and SiFive is unclear on simply what Horse Creek can be. Intel typically reserves the “Creek” names for socketed platforms fairly than all-in-one system on chip (SoC) boards. This means that, in all probability, the P550 can be restricted to supervisory or administration duties inside x86_64 Horse Creek CPUs fairly than straight processing directions from software program working on that platform.

Anandtech’s Ian Cuttress factors out that constructing the P550 straight into Horse Creek—which can be constructed on Intel’s latest 7nm course of node—would possibly present Intel with easier testing and extra fast improvement of the brand new 7nm course of itself.

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